1. Field of the Invention
This invention relates generally to integrated circuits more particularly, to a method of accurately determining propagation delays through multiplexers used in such circuits.
2. DESCRIPTION OF THE RELATED ART
In high speed integrated circuit design, e.g., the design of microprocessors, performance verification of the circuit design is accomplished by using timing analyzers which simulate the operation of the product being designed. Such analyzers function, for example, to calculate the amount of time that it takes for a particular signal to be propagated from a first circuit location to a second circuit location. In performing that function, the analyzers calculate the propagation delays through the individual circuit devices in the path between the first and second circuit locations.
One type of circuit device that is very commonly used in high speed integrated circuit design is a digital multiplexer composed of either passgates or tristate gates. A multiplexer has a plurality of sets of data input signals and a plurality of control signal inputs. The logic states of the control signal inputs determine which set of data input signals appear at the output of the device at any particular time. For example, the 2.times.1 multiplexer shown in FIG. 1 has two sets of data input signals, I1 and I2, and two control signal inputs, C1 and C2. The value of the output of the multiplexer is the value of input 11 when the control signals C1 and C2 have logic states of "1" and "0," respectively. In order for the value of the output of the multiplexer to assume the value of data input I2, the control signal C1 is switched from a logic "1" to a logic "0" and the control signal C2 is switched from a logic "0" to a logic "1," as shown in FIG. 2.
In actual circuits, disabling control edge 200 of control input signal C1 can occur much later in time than the enabling control edge 201 of control input signal C2, as shown in FIG. 2. In other words, both passgates 101 and 102 in FIG. 1 are enabled for the period of time, t.sub.c, between the enabling edge 201 of control input signal C2 and the disabling edge 200 of control signal C1, which results in a large contention current flowing through passgates 100 and 101 during the time t.sub.c. Until control signal C1 actually turns off, control signal C2 cannot drive a proper value to the output of the multiplexer. Thus, the time at which the value of the output of the multiplexer is the value of input I2 has been "pushed out" from the leading edge of control signal C2.
Heretofore, static timing analyzers have only used the enabling edge of control signals to determine when to propagate the output of a multiplexer and have ignored the potential interaction described above between the disabling edge of a control signal and the enabling edge of a control signal. Accordingly, critical timing paths and functional race conditions may have been missed.